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Data Sheet
ADE7854/ADE7858/ADE7868/ADE7878
Figure 44 shows the mechanism of the zero-crossing timeout
detection when the voltage or the current signal stays at a fixed
dc level for more than 62.5 μs × ZXTOUT μs.
A, B, C PHASE
PHASE A
PHASE C
PHASE B
VOLTAGES AFTER
16-BIT INTERNAL
REGISTER VALUE
ZXTOUT
LPF1
VOLTAGE
BIT 19 (SEQERR) IN
STATUS1 REGISTER
ZX A
ZX C
ZX B
OR
CURRENT
SIGNAL
0V
IRQ1
STATUS1[19] SET TO 1
STATUS1[19] CANCELLED
BY A WRITE TO THE
STATUS1 REGISTER WITH
ZXZOxy FLAG IN
STATUS1[31:0], x = V, A
y = A, B, C
IRQ1 INTERRUPT PIN
Figure 44. Zero-Crossing Timeout Detection
Phase Sequence Detection
The ADE7854 / ADE7858 / ADE7868 / ADE7878 have on-chip
phase sequence error detection circuits. This detection works
on phase voltages and considers only the zero crossings
determined by their negative-to-positive transitions. The regular
succession of these zero-crossing events is Phase A followed by
Phase B followed by Phase C (see Figure 46). If the sequence of
zero-crossing events is, instead, Phase A followed by Phase C
followed by Phase B, then Bit 19 (SEQERR) in the STATUS1
register is set.
If Bit 19 (SEQERR) in the MASK1 register is set to 1 and a
phase sequence error event is triggered, the IRQ1 interrupt pin
is driven low. The status bit is cleared and the IRQ1 pin is set
high by writing to the STATUS1 register with the Status Bit 19
(SEQERR) set to 1.
The phase sequence error detection circuit is functional only
when the ADE78xx is connected in a 3-phase, 4-wire, three voltage
sensors configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE
register, set to 00). In all other configurations, only two voltage
sensors are used; therefore, it is not recommended to use the
SEQERR BIT SET
Figure 45. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by
Phase C Voltage
Once a phase sequence error has been detected, the time
measurement between various phase voltages (see the Time
Interval Between Phases section) can help to identify which
phase voltage should be considered with another phase current
in the computational datapath. Bits[9:8] (VTOIA[1:0]), Bits[11:10]
(VTOIB[1:0]), and Bits[13:12] (VTOIC[1:0]) in the CONFIG
register can be used to direct one phase voltage to the datapath
of another phase. See the Changing Phase Voltage Datapath
section for details.
Time Interval Between Phases
The ADE7854 / ADE7858 / ADE7868 / ADE7878 have the capa-
bility to measure the time delay between phase voltages, between
phase currents, or between voltages and currents of the same
phase. The negative-to-positive transitions identified by the zero-
crossing detection circuit are used as start and stop measuring
points. Only one set of such measurements is available at one time,
based on Bits[10:9] (ANGLESEL[1:0]) in the COMPMODE
register.
PHASE A PHASE B PHASE C
detection circuit. In these cases, use the time intervals between
ZX A
ZX B
ZX C
phase voltages to analyze the phase sequence (see the Time
Interval Between Phases section for details).
Figure 45 presents the case in which Phase A voltage is not
followed by Phase B voltage but by Phase C voltage. Every time
a negative-to-positive zero crossing occurs, Bit 19 (SEQERR) in
the STATUS1 register is set to 1 because such zero crossings on
Phase C, Phase B, or Phase A cannot come after zero crossings
from Phase A, Phase C, or respectively, Phase B zero crossings.
Figure 46. Regular Succession of Phase A, Phase B, and Phase C
When the ANGLESEL[1:0] bits are set to 00, the default value,
the delays between voltages and currents on the same phase are
measured. The delay between Phase A voltage and Phase A
current is stored in the 16-bit unsigned ANGLE0 register (see
Figure 47 for details). In a similar way, the delays between voltages
and currents on Phase B and Phase C are stored in the ANGLE1
and ANGLE2 registers, respectively.
Rev. H | Page 35 of 100
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